Thiết kế số với VHDL qua các ví dụ

natorial circuits with registered outputs? 
Method 2: Sensitivity list 
entity RegisteredCircuit is 
 port (A,B,C,D,Clk: in std_logic; 
 Z: out std_logic); 
end entity RegisteredCircuit; 
architecture RTL of RegisteredCircuit is 
begin 
 process (A,B,C,D,Clk) is 
 begin 
 if (Clk’event and Clk=‘1’) then 
 -- combinatorial circuit 
 Z <= (A and B) or (C and D); 
 end if; 
 end process; 
end architecture RTL; 
A 
B 
C 
D 
Z 
‘if Clk’event’ has to be 
first line of process, 
with the description 
of the combinatorial 
circuit in the THEN 
part and with no 
ELSE part 
Dr. Le Dung Hanoi University of Science and Technology 
Rising clock edge 
How do we describe flip-flops with asynchronous reset? 
entity DFlipFlop is 
 port (D,Clk, Reset: in std_logic; 
 Q: out std_logic); 
end entity DFlipFlop; 
architecture RTL of DFlipFlop is 
begin 
 process (D, Clk, Reset) is 
 begin 
 if (Reset = ‘1’) then 
 Q <= ‘0’; 
 elseif (Clk’event and Clk=‘1’) then 
 Q <= D; 
 end if; 
 end process; 
end architecture RTL; 
Dr. Le Dung Hanoi University of Science and Technology 
Rising clock edge 
How do we describe flip-flops with synchronous reset? 
entity DFlipFlop is 
 port (D,Clk, Reset: in std_logic; 
 Q: out std_logic); 
end entity DFlipFlop; 
architecture RTL of DFlipFlop is 
begin 
 process (D, Clk, Reset) is 
 begin 
 if (Clk’event and Clk=‘1’) then 
 if (Reset=‘1’) then 
 Q <= 0; 
 else 
 Q <= D; 
 end if; 
 end if; 
 end process; 
end architecture RTL; 
Dr. Le Dung Hanoi University of Science and Technology 
Dr. Le Dung Hanoi University of Science and Technology 
Mô hình Moore FSM 
Present State 
Register 
Next State 
function 
Output 
function 
Inputs 
Present State 
Next State 
Outputs 
clock 
reset 
concurrent 
statements 
process(clock, reset) 
Dr. Le Dung Hanoi University of Science and Technology 
VÍ DỤ : Moore FSM 
•  Moore FSM that Recognizes Sequence “10” 
S0 / 0 S1 / 0 S2 / 1 
0 
0 
0 
1 
1 
1 
reset 
VÍ DỤ : Moore FSM in VHDL (1) 
TYPE state IS (S0, S1, S2); 
SIGNAL Moore_state: state; 
U_Moore: PROCESS (clock, reset) 
BEGIN 
 IF(reset = ‘1’) THEN 
 Moore_state <= S0; 
 ELSIF (clock = ‘1’ AND clock’event) THEN 
 CASE Moore_state IS 
 WHEN S0 => 
 IF input = ‘1’ THEN 
 Moore_state <= S1; 
 ELSE 
 Moore_state <= S0; 
 END IF; 
Dr. Le Dung Hanoi University of Science and Technology 
VÍ DỤ : Moore FSM in VHDL (2) 
 WHEN S1 => 
 IF input = ‘0’ THEN 
 Moore_state <= S2; 
 ELSE 
 Moore_state <= S1; 
 END IF; 
 WHEN S2 => 
 IF input = ‘0’ THEN 
 Moore_state <= S0; 
 ELSE 
 Moore_state <= S1; 
 END IF; 
 END CASE; 
 END IF; 
END PROCESS; 
Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’; 
Dr. Le Dung Hanoi University of Science and Technology 
Dr. Le Dung Hanoi University of Science and Technology 
Mô hình Mealy FSM 
Next State 
function 
Output 
function 
Inputs 
Present State Next State 
Outputs 
Present State 
Register 
clock 
reset 
process(clock, reset) 
concurrent 
statements 
VÍ DỤ : Mealy FSM 
•  Mealy FSM that Recognizes Sequence “10” 
S0 S1 
0 / 0 1 / 0 1 / 0 
0 / 1 reset 
Dr. Le Dung Hanoi University of Science and Technology 
VÍ DỤ : Mealy FSM in VHDL (1) 
TYPE state IS (S0, S1); 
SIGNAL Mealy_state: state; 
U_Mealy: PROCESS(clock, reset) 
BEGIN 
 IF(reset = ‘1’) THEN 
 Mealy_state <= S0; 
 ELSIF (clock = ‘1’ AND clock’event) THEN 
 CASE Mealy_state IS 
 WHEN S0 => 
 IF input = ‘1’ THEN 
 Mealy_state <= S1; 
 ELSE 
 Mealy_state <= S0; 
 END IF; 
Dr. Le Dung Hanoi University of Science and Technology 
VÍ DỤ : Mealy FSM in VHDL (2) 
 WHEN S1 => 
 IF input = ‘0’ THEN 
 Mealy_state <= S0; 
 ELSE 
 Mealy_state <= S1; 
 END IF; 
 END CASE; 
 END IF; 
END PROCESS; 
Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’; 
Dr. Le Dung Hanoi University of Science and Technology 
VÍ DU: Moore FSM – State diagram 
C z 1 = ⁄ 
resetn 
B z 0 = ⁄ A z 0 = ⁄ w 0 = 
w 1 = 
w 1 = 
w 0 = 
w 0 = w 1 = 
Dr. Le Dung Hanoi University of Science and Technology 
Present Next state Output 
state w = 0 w = 1 z 
A A B 0 
B A C 0 
C A C 1 
VÍ DỤ: Moore FSM – State table 
Dr. Le Dung Hanoi University of Science and Technology 
VÍ DỤ: Moore FSM – Building Block 
Present State 
Register 
Next State 
function 
Output 
function 
Input: w 
Present State: y 
Next State 
Output: z 
clock 
resetn 
process(clock, reset) 
concurrent 
statements 
Dr. Le Dung Hanoi University of Science and Technology 
USE ieee.std_logic_1164.all ; 
ENTITY simple IS 
 PORT ( clock : IN STD_LOGIC ; 
 resetn : IN STD_LOGIC ; 
 w : IN STD_LOGIC ; 
 z : OUT STD_LOGIC ) ; 
END simple ; 
ARCHITECTURE Behavior OF simple IS 
 TYPE State_type IS (A, B, C) ; 
 SIGNAL y : State_type ; 
BEGIN 
 PROCESS ( resetn, clock ) 
 BEGIN 
 IF resetn = '0' THEN 
 y <= A ; 
 ELSIF (Clock'EVENT AND Clock = '1') THEN 
VÍ DỤ: Moore FSM in VHDL (1) 
Dr. Le Dung Hanoi University of Science and Technology 
 CASE y IS 
 WHEN A => 
 IF w = '0' THEN 
 y <= A ; 
 ELSE 
 y <= B ; 
 END IF ; 
 WHEN B => 
 IF w = '0' THEN 
 y <= A ; 
 ELSE 
 y <= C ; 
 END IF ; 
 WHEN C => 
 IF w = '0' THEN 
 y <= A ; 
 ELSE 
 y <= C ; 
 END IF ; 
 END CASE ; 
VÍ DỤ: Moore FSM in VHDL (2) 
Dr. Le Dung Hanoi University of Science and Technology 
 END IF ; 
 END PROCESS ; 
 z <= '1' WHEN y = C ELSE '0' ; 
END Behavior ; 
A 
w 0 = z 0 = ⁄ 
w 1 = z 1 = ⁄ B w 0 = z 0 = ⁄ 
resetn 
w 1 = z 0 = ⁄ 
VÍ DỤ: Mealy FSM - State diagram 
Dr. Le Dung Hanoi University of Science and Technology 
Present Next state Output z 
state w = 0 w = 1 w = 0 w = 1 
A A B 0 0 
B A B 0 1 
VÍ DỤ: Mealy FSM – State table 
Dr. Le Dung Hanoi University of Science and Technology 
process(clock, reset) 
Next State 
function 
Output 
function 
Input: w 
Present State: y Next State 
Output: z 
Present State 
Register 
clock 
resetn 
concurrent 
statements 
VÍ DỤ: Mealy FSM – Building Block 
Dr. Le Dung Hanoi University of Science and Technology 
LIBRARY ieee ; 
USE ieee.std_logic_1164.all ; 
ENTITY Mealy IS 
 PORT ( clock : IN STD_LOGIC ; 
 resetn : IN STD_LOGIC ; 
 w : IN STD_LOGIC ; 
 z : OUT STD_LOGIC ) ; 
END Mealy ; 
ARCHITECTURE Behavior OF Mealy IS 
 TYPE State_type IS (A, B) ; 
 SIGNAL y : State_type ; 
BEGIN 
 PROCESS ( resetn, clock ) 
 BEGIN 
 IF resetn = '0' THEN 
 y <= A ; 
 ELSIF (clock'EVENT AND clock = '1') THEN 
VÍ DỤ: Mealy FSM in VHDL code (1) 
Dr. Le Dung Hanoi University of Science and Technology 
VÍ DỤ: Mealy FSM in VHDL code (2) 
 CASE y IS 
 WHEN A => 
 IF w = '0' THEN 
 y <= A ; 
 ELSE 
 y <= B ; 
 END IF ; 
 WHEN B => 
 IF w = '0' THEN 
 y <= A ; 
 ELSE 
 y <= B ; 
 END IF ; 
 END CASE ; 
Dr. Le Dung Hanoi University of Science and Technology 
 END IF ; 
 END PROCESS ; 
 WITH y SELECT 
 z <= w WHEN B, 
 z <= ‘0’ WHEN others; 
END Behavior ; 
VÍ DỤ: Mô hình FSM kiểu thanh ghi trạng thái 
Wait 
00 
Up1 
01 
Up2 
10 
Up3 
11 
Down3 
11 
Down2 
10 
Down1 
01 
Start=0 
Start=1 
Up=0 
Start=1 
Up=1 
Up Start 
Next 
state 
logic 
Out 
put 
logic 
State 
Reg 
Reset 
Output 
NextState 
CurrentState 
Dr. Le Dung Hanoi University of Science and Technology 
Wait 
00 
Up1 
01 
Up2 
10 
Up3 
11 
Down3 
11 
Down2 
10 
Down1 
01 
Start=0 
Start=1 
Up=0 
Start=1 
Up=1 
entity FSM is 
 port ( Start, Up, Reset, Clk: in std_logic; 
 Output: out std_logic_vector(0 to 1)); 
end entity FSM; 
architecture Behav of FSM is 
 type FSM_States = (Wait,Up1,Up2, 
 Up3,Down1,Down2,Down3); 
 signal CurrentState, NextState : FSM_States; 
begin 
 OutputLogic: 
 process(CurrentState) is 
 end process OutputLogic; 
 NextStateLogic: 
 process(CurrentState,Start,Up) is 
 end process NextStateLogic; 
 StateRegister: 
 process(NextState,Clk,Reset) is 
 end process StateRegister; 
end architecture Behav; 
VÍ DỤ: Mô hình FSM kiểu thanh ghi trạng thái 
Dr. Le Dung Hanoi University of Science and Technology 
OutputLogic: 
process(CurrentState) is 
begin 
 case CurrentState is 
 when Wait => 
 Output <= “00”; 
 when Up1|Down1 => 
 Output <= “01”; 
 when Up2|Down2 => 
 Output <= “10”; 
 when Up3|Down3 => 
 Output <= “11”; 
 end case; 
end process OutputLogic; 
Wait 
00 
Up1 
01 
Up2 
10 
Up3 
11 
Down3 
11 
Down2 
10 
Down1 
01 
Start=0 
Start=1 
Up=0 
Start=1 
Up=1 
VÍ DỤ: Mô hình FSM kiểu thanh ghi trạng thái 
Dr. Le Dung Hanoi University of Science and Technology 
NextStateLogic: 
process(CurrentState,Start,Up) is 
begin 
 case CurrentState is 
 when Wait => 
 if (Start=‘0’) then 
 NextState <= Wait; 
 elseif (Up=‘1’) then 
 NextState <= Up1; 
 else 
 NextState <= Down3; 
 end if; 
 when Up1 => 
 NextState <= Up2; 
 when Up2 => 
 NextState <= Up3; 
 when Up3|Down1 => 
 NextState <= Wait; 
 when Down3 => 
 NextState <= Down2; 
 when Down2 => 
 NextState <= Down1; 
 end case; 
end process NextStateLogic; 
VÍ DỤ: Mô hình FSM kiểu thanh ghi trạng thái 
Wait 
00 
Up1 
01 
Up2 
10 
Up3 
11 
Down3 
11 
Down2 
10 
Down1 
01 
Start=0 
Start=1 
Up=0 
Start=1 
Up=1 
Dr. Le Dung Hanoi University of Science and Technology 
StateRegister: 
process(NextState,Clk,Reset) is 
begin 
 if Reset=‘1’ then 
 CurrentState <= Wait; 
 elseif (Clk’event and Clk=‘1’) then 
 CurrentState <= NextState; 
 end if; 
end process StateRegister; 
VÍ DỤ: Mô hình FSM kiểu thanh ghi trạng thái 
Wait 
00 
Up1 
01 
Up2 
10 
Up3 
11 
Down3 
11 
Down2 
10 
Down1 
01 
Start=0 
Start=1 
Up=0 
Start=1 
Up=1 
Dr. Le Dung Hanoi University of Science and Technology 
Dr. Le Dung Hanoi University of Science and Technology