Bài giảng Kỹ thuật số - Chương 6: VHDL

Updn
Clk
Q0
Updncnt4
Rst
Q1
Q2
Q3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sipo IS
GENERIC (n: NATURAL := 8);
PORT (Serin, Clk : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(
n-1 downto 0));
END sipo;
ARCHITECTURE shiftreg OF sipo IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
reg <= reg(n-2 downto 0) & Serin;
END IF; 
END PROCESS; 
Q <= reg;
END shiftreg;
Thanh ghi dòch (shift reg.)
NguyenTrongLuat 84
S
I
P
O
Serin
Clk
Q
sipo
n
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY siso IS
GENERIC (n : NATURAL := 8);
PORT (Clk, Serin : IN STD_LOGIC;
Serout : OUT STD_LOGIC);
END siso;
ARCHITECTURE shiftreg OF siso IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
reg <= reg(n-2 downto 0) & Serin;
END IF;
END PROCESS; 
Serout <= reg(n-1);
END shiftreg;
NguyenTrongLuat 85
S
I
S
O
Serin
Clk
siso
Serout
O
NguyenTrongLuat 86
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY piso IS
GENERIC (n: NATURAL := 8);
PORT (Serin, Clk, ShLd : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(n-1 downto 0);
Serout : OUT STD_LOGIC);
END piso;
ARCHITECTURE shiftreg OF piso IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
IF ShLd = ’0’ THEN
reg <= D;
ELSE reg <= reg(n-2 downto 0) & Serin;
END IF; 
END PROCESS; 
Serout <= reg(n-1);
END shiftreg;
S
I
P
D
Clk
Serout
piso
n
ShLd
Serin
- Maùy traïng thaùi höõu haïn ñöôïc thieát keá deã daøng baèng phaùt
bieåu PROCESS.
- Vieäc chuyeån traïng thaùi ñöôïc moâ taû trong Process vôùi danh
saùch caûm nhaän (sensitivity list) laø clock vaø tín hieäu reset baát
ñoàng boä.
- Ngoõ ra coù theå ñöôïc moâ taû baèng caùc phaùt bieåu ñoàng thôøi
(concurrenrt) naèm ngoaøi process.
- Coù 2 kieåu FSM: MOORE vaø MEALY
NguyenTrongLuat 87
MAÙY TRAÏNG THAÙI
FSM
MOORE 
FSM
Present State
Register
Next State
function
Output
function
Inputs
Present StateNext State
Outputs
clock
reset
Next state function: haøm traïng thaùi keá tieáp laø maïch toå hôïp phuï
thuoäc vaøo ngoõ vaøo vaø traïng thaùi hieän taïi
Output function: haøm ngoõ ra laø maïch toå hôïp phuï thuoäc vaøo traïng
thaùi hieän taïi
Present State Register: thanh ghi traïng thaùi hieän taïi löu giöõ 1 
traïng thaùi hieän taïi, seõ chuyeån traïng thaùi khi coù xung clock.
NguyenTrongLuat 88
Present State
Register
Next State
function
Output
function
Inputs
Present StateNext State
Outputs
clock
reset
Process Thanh ghi traïng thaùi:
PROCESS (reset, clock)
Process Haøm traïng thaùi keá tieáp:
PROCESS (input, present_state)
Process Haøm ngoõ ra:
PROCESS (present_state)
Concurrent Statements
FSM kieåu MOORE ñöôïc moâ taû baèng 3 PROCESS
- Process Haøm ngoõ ra coù theå thay theá baèng caùc phaùt bieåu
ñoàng thôøi (concurrent statement)
NguyenTrongLuat 89
- Process 2 vaø 3 coù theå keát hôïp thaønh 1 Process.
LIBRARY ieee;
USE iee.std_logic_1164.all;
ENTITY Moore_FSM IS
PORT (clock, rerset, input: IN std_logic;
output: OUT std_logic);
END Moore_FSM;
ARCHITECTURE behavior OF Moore_FSM IS
TYPE state IS (list of states);
SIGNAL pr_state, nx_state: state;
BEGIN
PROCESS(clk, reset)
BEGIN
IF reset = ’1’ THEN
pr_state <= reset state;
ELSIF (clock = ’1’ and clock’event) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
TYPE state IS (list of states): khai baùo state laø döõ lieäu kieåu lieät keâ
NguyenTrongLuat 90
Process Thanh ghi traïng thaùi:
PROCESS (reset, clock)
PROCESS (input, ps_state )
CASE ps_state IS
WHEN state_1 =>
IF input = ’’ THEN
nx_state <= state_2;
ELSIF nx_state <= state_3;
END IF;
WHEN state_2 =>
IF input = ’’ THEN
nx_state <= state_1;
ELSIF nx_state <= state_3;
END IF;
. . .
END CASE;
END PROCESS;
NguyenTrongLuat 91
Process Haøm traïng thaùi keá tieáp:
PROCESS (input, present_state)
PROCESS(ps_state )
CASE ps_state IS
WHEN state_1 =>
output <= ’...’;
WHEN state_2 =>
output <= ’...’;
...
END CASE;
END PROCESS;
Coù theå duøng phaùt bieåu IF  THEN 
NguyenTrongLuat 92
Process Haøm ngoõ ra:
PROCESS (present_state)
Coù theå thay theá process naøy baèng phaùt bieåu ñoàng thôøi
output <= ... ;
TT 
hieän taïi
TT keá tieáp Ngoõ ra
(z)x = 0 x = 1
LIBRARY ieee;
USE iee.std_logic_1164.all;
ENTITY Moore_FSM IS
PORT (
clock, rerset, x: IN std_logic;
z: OUT std_logic);
END Moore_FSM;
ARCHITECTURE behavior OF Moore_FSM IS
TYPE state IS (S0, S1, S2, S3);
SIGNAL pr_state, nx_state: state;
BEGIN
regst: PROCESS(clk, reset)
BEGIN
IF reset = ’1’ THEN pr_state <= S0;
ELSIF (clock = ’1’ and clock’event) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
NguyenTrongLuat 93
nxst: PROCESS (x, ps_state )
CASE ps_state IS
WHEN S0 => 
IF x = ’0’ THEN
nx_state <= S0;
ELSIF nx_state <= S1;
END IF;
WHEN S1 =>
IF x = ’0’ THEN nx_state <= S2;
ELSIF nx_state <= S1;
END IF;
WHEN S2 =>
IF x = ’0’ THEN nx_state <= S0;
ELSIF nx_state <= S3;
END IF;
WHEN S3 =>
IF x = ’0’ THEN nx_state <= S2;
ELSIF nx_state <= S1;
END IF;
END CASE;
END PROCESS;
TT 
hieän taïi
TT keá tieáp Ngoõ ra
(z)x = 0 x = 1
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
NguyenTrongLuat 94
TT 
hieän taïi
TT keá tieáp Ngoõ ra
(z)x = 0 x = 1
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
Output: PROCESS(ps_state )
CASE ps_state IS
WHEN S3 =>
z <= ’1’;
WHEN OTHERS =>
z <= ’0’;
END CASE;
END PROCESS;
END behavior;
Output: PROCESS(ps_state )
IF ps_state = S3 THEN z <= ’1’;
ELSE ’0’;
END IF;
z <= ’1’ WHEN ps_state = S3 ELSE ’0’;
NguyenTrongLuat 95
Söû duïng
IFTHEN
Dùng phát biểu
đồng thời
NguyenTrongLuat 96
Keát hôïp Process 2 vaø 3 thaønh 1 Process
TT 
hieän taïi
TT keá tieáp Ngoõ ra
(z)x = 0 x = 1
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
nx_out: PROCESS (x, ps_state )
CASE ps_state IS
WHEN S0 => 
z <= ’0’;
IF x = ’0’ THEN
nx_state <= S0;
ELSIF nx_state <= S1;
END IF;
WHEN S1 =>
z <= ’0’;
IF x = ’0’ THEN nx_state <= S2;
ELSIF nx_state <= S1; END IF;
WHEN S2 =>
z <= ’0’;
IF x = ’0’ THEN nx_state <= S0;
ELSIF nx_state <= S3; END IF;
WHEN S3 =>
z <= ’1’;
IF x = ’0’ THEN nx_state <= S2;
ELSIF nx_state <= S1; END IF;
END CASE;
END PROCESS;
END behavior;
Present State
Present State
Register
Next State
function
Output
function
Inputs
Next State
Outputs
clock
reset Process Thanh ghi traïng thaùi:
PROCESS (reset, clock)
Process Haøm traïng thaùi keá tieáp
vaø Ngoõ ra:
PROCESS (input, present_state)
FSM kieåu MEALY ñöôïc moâ taû baèng 2 PROCESS
NguyenTrongLuat 97
MEALY 
FSM
PROCESS (input, ps_state )
CASE ps_state IS
WHEN state_1 =>
IF input = ’’ THEN
output <= ’...’;
nx_state <= state_2;
ELSIF 
output <= ’...’;
nx_state <= state_3;
END IF;
. . .
END CASE;
END PROCESS;
NguyenTrongLuat 98
Process Haøm traïng thaùi keá tieáp vaø Ngoõ ra:
PROCESS (input, present_state)
nx_out: PROCESS (x, ps_state )
CASE ps_state IS
WHEN S0 => 
IF x = ’0’ THEN 
z <= ’0’;
nx_state <= S0;
ELSIF 
z <= ’0’;
nx_state <= S1;
END IF;
WHEN S1 =>
IF x = ’0’ THEN 
z <= ’0’;
nx_state <= S2;
ELSIF 
z <= ’0’;
nx_state <= S1; 
END IF;
WHEN S2 =>
IF x = ’0’ THEN 
z <= ’0’;
nx_state <= S2;
ELSIF 
z <= ’0’;
nx_state <= S1; 
END IF;
END CASE;
END PROCESS;
TT 
HT
TT keá tieáp Ngoõ ra (Z)
X = 0 1 X = 0 1
S0
S1
S2
S0
S2
S2
S1
S1
S1
0
0
0
0
0
1
NguyenTrongLuat 99
- Vieäc gaùn traïng thaùi thöôøng laø töï ñoäng. 
- Ta coù 2 caùch ñeå gaùn cho moãi traïng thaùi baèng 1 toå hôïp nhò phaân:
TYPE state IS (S0, S1, S2);
SIGNAL pr_state, nx_state: state;
TYPE state IS STD_LOGIC_VECTOR(1 downto 0);
CONSTANT S0: state:= ”00”;
CONSTANT S1: state:= ”01”;
CONSTANT S2: state:= ”11”;
SIGNAL pr_state, nx_state: state;
* Söû duïng thuoäc tính (attribute) enum_encoding:
TYPE state IS (S0, S1, S2);
ATTRIBUTE ENUM_ENCODING: STRING;
ATTRIBUTE ENUM_ENCODING OF state: TYPE IS ”00 01 11”;
SIGNAL pr_state, nx_state: state;
Gán trạng thái
* Khai baùo constant
NguyenTrongLuat
Phaùt bieåuWAIT
- WAIT laø phaùt bieåu tuaàn töï (sequential statement). 
- Neáu Process khoâng coù danh saùch caûm nhaän (sensitivity list) 
thì phaùt bieåu WAIT laø phaùt bieåu ñaàu tieân cuûa Process
WAIT UNTIL condition_signal;
WAIT ON sensitivity_list; 
WAIT FOR time; 
Process ñöôïc thöïc thi khi coù söï thay ñoåi giaù trò cuûa 1 hoaêc
nhieàu tín hieäu trong danh saùch caûm nhaän
Process ñöôïc thöïc thi khi coù ñieàu kieän cuûa 1 tín hieäu xaåy ra
(true)
Chæ duøng trong moâ phoûng (testbench). Taïm döøng thöïc hieän
Process trong 1 khoaûng thôøi gian (time).
NguyenTrongLuat
NguyenTrongLuat
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Dlatch IS
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END Dlatch;
ARCHITECTURE behavior OF Dlatch IS
BEGIN
PROCESS (D, Clk)
BEGIN
IF Clk = ’1’ THEN 
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
ARCHITECTURE behavior OF Dlatch IS
BEGIN
PROCESS 
BEGIN
WAIT ON Clk, D;
IF Clk = ’1’ THEN 
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
D
Clk
Q
Q
Dlatch
NguyenTrongLuat
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Dflipflop IS
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END Dflipflop;
ARCHITECTURE behavior OF Dflipflop IS
BEGIN
PROCESS (Clk)
BEGIN
IF Clk’event AND Clk = ’1’ THEN 
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
ARCHITECTURE behavior OF Dflipflop IS
BEGIN
PROCESS 
BEGIN
WAIT UNTIL Clk’event AND Clk = ’1’; 
Q <= D; Qn <= NOT Q;
END PROCESS;
END behavior;
D
clk
Q
Q
Dflipflop