The uA741 Operational Amplifier

BME K54
Nguyễn Trung Hiếu
Nguyễn Văn Tú	 
The uA741 Operational Amplifier
Schematic
Stages
The input differential stage
Consists of transistors Q1 through Q7 with biasing performed by Q8, Q9, Q10
Q1 and Q2: are emitter followers which cause the high input resistance and deliver the differential input signal to the common base amplifier formed by Q3 and Q4.
Transistors Q5, Q6, Q7 and resistors R1, R2, R3 form the load circuit of the input stage, provides a high resistance load
In the 741, the level shifting is done in the first stage using the lateral pnp transistors Q3, Q4 → protection of the input stage transistors Q1, Q2 against emitter-base junction break down. (Level shifting: to shift the dc level of the signal so that the signal at the op-amp output can swing positive and negative.)
The intermediate single-ended high-gain stage
The intermediate stage is composed of Q16, Q17, Q13B and R8, R9 
Transistor Q16 acts as emitter follower, giving high input resistance 
Q17 is a common-emitter amplifier with R8=100Ω in the emitter. The load of this amplifier is composed of the output resistance of Q13B. Using a transistor current source as a load resistance is called active load
The output of this amplifier (the collector of Q17) has a feedback loop through Cc. This capacitor causes the op-amp to have a pole at about 4Hz. 
The output –buffering stage.
The output stage consists of the complimentary pair Q14 and Q20, and a class AB output stage composed of Q18 and Q19. Q15 and Q21 give short circuit protection (described later) and Q13A supplies current to the output stage.
The purpose of the output stage is to provide the amplifier with a low output resistance. In addition, the output stage should be able to supply relatively large load currents. The 741 uses an effective output circuit known as class AB output stage.
In class-AB operation, each device operates the same way as in class B over half the waveform, but also conducts a small amount on the other half. As a result, the region where both devices simultaneously are nearly off is reduced. The result is that when the waveforms from the two devices are combined, the crossover is greatly minimized or eliminated altogether.
Class AB sacrifices some efficiency over class B in favor of linearity; it is typically much more efficient than class A. Class-B amplifiers only amplify half of the input wave cycle, thus creating a large amount of distortion
This stage is driven by the second stage transistor Q17, an emitter follower Q23 and loaded by R12. As said before the circuit is of the AB class, with the network composed of Q18, Q19 and R10 providing the bias of the output transistors Q14 and Q20.
Short circuit protection
Transistors Q11 and Q12 form one half of a current mirror that is used to supply current to the entire op-amp
Transistor Q10 is used to supply a bias current to the input stage, Q13B supplies the second stage, and Q13A supplies the output stage
Transistors Q15, Q21, Q24, Q22, and resistors R6, R7, and R11 make up the short circuit protection circuit.
DC Analysis
Reference bias current
Generates the reference bias current through R5
The opAmp reference current is given by: 
For and , we have 
Input-Stage bias:
From this value of , the current in the collector of Q10 can be calculated:
This equation can be solved by trial and error to determine:
From symmetry, we see that : 
If npn is hight, then :
And the base current of Q3 and Q4 are equal, with a value of , where denotes of the pnp devices
The current mirror by Q8, Q9 is fed by an input current of 2I. We have output current of the mirror:
If then 
We determine that:
If we neglect the base current of Q16 and Q7, then
 , 
So, the bias current of Q7:
Input Bias and Ofset Currets
Input bias current is 
For the 741:
= 200, yields 47.5nA
The input offset current :
Input Ofset Voltage
The Input ofset Voltage is due to mismatches between Q1 and Q2, between Q3 and Q4 , between Q5 and Q6 , and between R1 and R2. Evaluation of the components of VOS corresponding to the various mismatches. We find the current that results at the output of the first stage due to the particular mismatch being considered. Then we find the differential input voltage that must be applied to reduce the output current to zero. 
Input common –mode range
The Input common –mode range is the range on input common mode voltages over which the input stage remains in the linear active mode. In the 741 circuit the input common mode range is determined at the upper end by saturation of Q1 and Q2 and at the lower end by saturation Q3 and Q4.
Second Stage Bias
If we neglect the the base current of Q23:
IC17= I13B
Because Q13B has o scale current 0,75 times that of Q12,then IC13B ≃ 0,75 IREF
IC13B = 550 µA , IC17 ≃ 550 µA
VBE17= VT × lnIC17 IS = 618 mV
IC16 ≃ IB17 + IE17R8+ VBE17R9 =16,2 µA 
Output stage bias
Because IS of Q13A is 0,25 times the IS of Q12,so the current source of Q13A delivers a current of 0,25 IREF to the network composed of Q18, Q19, Q10.
If we neglect the base current of Q14, Q20 then:
IC23 ≃ IE23 ≃ IREF= 180 µA
IB23 = 180/50 = 3.6 µA
If we assume that VBE18 ≃ 0.6 V then IE18 = 180 – 15 = 165 µA
Also , IC18 ≃ IE18 = 165 µA and VBE18 =588 mV 
IB18 = 165/200 = 0.8 µA
IC19 ≃ IE19 = 15.8 µA 
The voltage drop across the base – emitter junction of Q19:
VBE19=VT × lnIC19 IS = 530 mV
The purpose of the Q18, Q19 network is to establish two VBE drops between the bases of the output transistors Q14 , Q20
VBB =VBE18 +VBE19 = 588 +530 = 1118 mV
We can calculate : VBB=VT × lnIC14 IS14 +VT × lnIC20 IS20
With IS19 =IS20 = 3 x 10-14 A
We have : IC14 = IC20=154 µA
Small signal analysis
The Input stage
Q1 and Q2 are connected to a constant DC voltage, they are show grounded
The constant current biasing of the bases of Q3 and Q4 à equivalent to have the common base terminal open - circuited 
Emitter signal current :
The input differential resistance of the op-amp: 
Neglect the signal current in base of Q7 and Q5, Q6 are identical
 IC5=IC6= ∝ie
The output current : 
io=2αie
The transconductance of the input stage :
Ro1=Ro4||Ro6
Ro4=ro4[1+gm (RE//rπ)] where RE=re=2.63kΩ, ro=VAI=50V9.5µA=5.26MΩ and neglect rπ → Ro4=10.5 MΩ
Ro6= ro61+gm × R2=18.2MΩ
R01=6.7MΩ
Second stage
The input resistance Ri2 :
 Ri2=(β16+1)[re16+R9//(β17+1)(re17+R8)]≅4MΩ
To determine the output resistance Ro2, we ground the input terminal and find the resistance looking back into the output terminal : Ro2=(Ro13B//Ro17).
For 741 components, we obtain that Ro13B=ro13B=90.9kΩ
Fig. Thévenin equivalent circuit to determine Ro17
R017=r017[1+gm (RE//rπ)]≅787kΩ → Ro2=81kΩ
Output stage
Fig. The model of the output stage
vo2=-Gm2Ro2vi2 (where Gm2=6.5(mA/V) , Ro2=81kΩ)
The voltage gain of the second stage : A2≡vi3vi2=-Gm2Ro2Ri3Ri3+Ro2
Assuming β20=50 and RL=2kΩ, the input resistance Rin of Q20 = β20×RL=100kΩ
(Rin of Q20) // (ro13A+R18-19network) where ro13A=280k and R18-19network=160Ω . It is very small.
Re23=(100k // 280k) ≈74k and Ri3≈β23×Re23=50×74k=3.7MΩ→A2=-515V/V
The voltage gain of the output stage: Gvo3=vovo2 (where RL=∞) . With RL=∞, the emitter resistance of Q23 is very large and Rinput of Q23 is very large → Gvo3≈1
Fig. circuit for finding the output resistance
 Ro23=Ro2β23+1+ re23 (where re23= VTIc23=250.18=139Ω)
Ro3= Ro23β20+1+ re20