Latches and Flip-Flops - Dr. Le Dung

1Latches and Flip-Flops
Dr. Le Dung
Faculty of Electronics and Telecommunications
Hanoi University of Science and Technology
Content
• Memory element
• Latches
• Flip-Flops
Dr. Le Dung 2 Hanoi University of Science and Technology
2A device with exactly two stable states
Bistable multivibrator circuit
Q1 on Æ Q2 off
Q1 off Æ Q2 on
2 stable states
as 
a memory element
can store one bit
Dr. Le Dung 3 Hanoi University of Science and Technology
Memory element
Latch Flip-Flop (with clock)
1-state
or 
0-state
Q
Q
Excitation 
inputs
1-state (set): 
Q=1, Q=0
0-state (reset):
Q=0, Q=1
Inhibited-state:
Q = Q
Set
Reset
Q
Set
Reset
Q
Clock
Excitation
inputs
Dr. Le Dung 4 Hanoi University of Science and Technology
3Latches
• SR latch (Set-Reset latch)
+ with NOR structure
+ with NAND structure 
• Gated SR latch
• D latch (Delay or Data latch = transparent latch)
• Some applications of the latches (1) (2) (3)
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Set-Reset Latch with NOR structure
S R Q’ (next)
0 0 Q (latch)*
0 1 0 (reset)
1 0 1 (set)
1 1 Q’=Q’=0
(Inhibited)
* Latch = No change
SR latch
S, R active “High”
NOR structure
Set
Q=1,Q=0
Reset
Q=0,Q=1
X
Q=Q
SR=10
SR=01
SR=00
SR=10
SR=00
SR=01
SR=11 SR=11
Inhibited
State diagram
(Moore)
Latch Latch
Dr. Le Dung 6 Hanoi University of Science and Technology
4Set-Reset Latch with NAND structure
S R Q’ (next)
0 0 Q’=Q’=1
(Inhibited)
0 1 1 (set)
1 0 0 (reset)
1 1 Q (latch)*
* Latch = No change
SR latch
S, R active “Low”
NAND structure
Set
Q=1,Q=0
Reset
Q=0,Q=1
X
Q=Q
SR=01
SR=10
SR=11
SR=01
SR=11
SR=10
SR=00 SR=00
Inhibited
State diagram
(Moore)
Latch Latch
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SR latch timing diagram
NOR SR Latch
S, R active “High”
Q’=Q’=0
(Inhibited)
11
1 (set)01
0 (reset)10
Q (latch)*00
Q’ (next)RS
(Illegal)
Q’ = S + RQ
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5Gated SR Latch
* Hold = No action
Gated SR latch
E S R Q’ (next)
0 x x Q (hold)*
1 0 0 Q (latch)
1 0 1 0 (reset)
1 1 0 1 (set)
1 1 1 Inhibited
E,S,R active “High”
Set
Q=1,Q=0
Reset
Q=0,Q=1
X
Q=Q
ESR=110
ESR=1010xx,110
111 111
Inhibited
State diagram
(Moore)
0xx,
101
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D Latch
E D Q’ (next)
0 x Q (hold)*
1 0 0 (reset=store 0)
1 1 1 (set=store 1)
Set
Q=1,Q=0
Reset
Q=0,Q=1
ED=11
ED=10
0x,
11
0x,
10
Store 1 Store 0
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Data or Delay latch
= transparent latch
6Some applications of the latches (1)
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(App 1) Debounce a mechanical switch
Some applications of the latches (2)
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(App 2) LED detect alarm system
7Some applications of the latches (3)
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(App 3) 74LS75 Quad D latch module with enable
Flip-Flops
• Clock signals
• Clocked flip-flops
+ Master-Slave Flip-Flop (Pulse-triggered FF)
+ Edge-triggered Flip-Flop
• SR Flip-Flop
• JK Flip-Flop
• D Flip-Flop
• T Flip-Flop
• Asynchronous set and reset (Preset and Clear)
• Some applications of the flip-flops(1) (2) (3)
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8Clock signals
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Clocked Flip-Flops
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9Master-Slave Flip-Flops
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Edge-triggered Flip-Flops
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PGT detector NGT detector
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SR Flip-Flop (active with PGT)
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SR Flip-Flop (active with NGT)
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JK Flip-Flop
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JK Flip-Flop (active with PGT)
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JK Flip-Flop (active with NGT)
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Internal Circuitry of JK Flip-Flop
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Feedback
Feedback
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Pulse-triggered JK Flip-Flop
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D Flip-Flop
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Make D Flip-Flop from JK Flip-Flop
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T Flip-Flop (active with NGT)
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Clocked T Flip-Flop
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Asynchronous set and reset (1)
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Asynchronous set and reset (2)
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JK-FF with Preset and Clear inputs
Asynchronous set and reset (3)
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Asynchronous set and reset (4)
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T-FF with Preset and Clear inputs
Applications of the Flip-Flop
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+ Thiết kế các bộ đếm (Counter)
+ Thiết kế thanh ghi dịch (Shift register)
+ Thiết kế mạch dãy
+ Các ứng dụng khác
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Some applications of the Flip-Flop (1)
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3 bits Up-Counter
Some applications of the Flip-Flop (2)
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Serial shift register