Language based HW design: VHDL

L Analog and Mixed Signal)IEEE standard 1076.1-1999is a super-set of the full IEEE VHDL 1076-1993 standard for digital design8VHDL primer: IntroductionAbstraction levelsBehavioralInterconnected functionsOnly info on functions or algorithms (what)Only timing needed to let the function work correctlyOK for VHDLBehavioral synthesisers immature; used for high level executable specification in top-down design and manual synthesis into RTL9VHDL primer: IntroductionAbstraction levelsRTLInterconnected registers and combinatorial unitsInfo on function (what) and architecture (how)Cycle accurateNo technology dependent timing infoOK for VHDLGood synthesisersGate levelInterconnected gates and flip-flopsInfo on function and architectureInfo on technology dependent timing (gate delays)LayoutInfo on layout on siliconContinuous timingAnalog effects10VHDL primer: IntroductionOther hardware description languages (HDL)VerilogMore widespread in USA than in EuropeOften required for gate level or RTL level ASIC sign-offNever ending discussion which is betterPLD languages like ABEL, PALASM, These are more at the gate level, capturing also technology dependent features (e.g. detailed timing)11VHDL primer: IntroductionDifference between HDLs and traditional software programming languagesConcurrency: all hardware components operate in parallelData types: support is needed for arbitrary size integers, bit vectors, fixed point numbersConcept of time12Language based HW design:a VHDL primerIntroductionA first look at VHDLSignals and data typesVHDL operatorsConcurrent versus sequential statementsSequential construction statementsHigher performance, less portability:e.g. synthesis issues for Xilinx13A First look at VHDL:Example 1 task descriptionDesign a circuit named ‘Test’ with 3 8-bit inputs (In1, In2, In3) and two boolean outputs (Out1, Out2). The first output equals ‘1’ when the first and second input are equal; the second output equals ‘1’ when the first and third input are equal.Let’s first make a schematic design:14A First look at VHDL:Schematic specificationThe circuit will be hierarchically decomposed into a top level component ‘Test’ containing 2 instantiations of a comparator component ‘Compare’In1In2In3TestOut1Out2CompareABEQCompareABEQ15ABEQCompareA First look at VHDL:Schematic specificationThe comparator is then hierarchically decomposed into a gate level combinatorial circuitA[0]B[0]A[1]B[1]A[7]B[7]EQXNORAND16A First look at VHDL:Entity and ArchitectureDeclaration of the ‘Compare’ design entity:-- Eight bit comparator--entity Compare is	port(	A,B: in bit_vector(0 to 7);	EQ: out bit);end entity Compare;architecture Behav1 of Compare isbegin	EQ X, B => Y, EQ => Z);	end for;	for others: Comparator use entity Compare(Behav1)	port map (A => X, B => Y, EQ => Z);	end for;	end for;end configuration Build1;Note: ‘configuration’ corresponds in SW to ‘linking’Both ‘use entity’s couldbe combined in one:for All: Comparator ...21A First look at VHDL:SyntaxENTITY:entity Entity_name is	port(	Signal_name: in Signal_type;	Signal_name: out Signal_type);end entity Entity_name;ARCHITECTURE:architecture Architecture_name of Entity_name is	local_signal_declarations;	component_declarations;begin	statements;end architecture Architecture_name;22A First look at VHDL:SyntaxCOMPONENT:component Component_name is	port(	Signal_name: in Signal_type;	Signal_name: out Signal_type);end component Component_name;COMPONENT INSTANTIATION:-- component instantiationInstance_name: component Component_name	port map (Signal_list);	or-- direct instantiationInstance_name: entity Entity_name(Architecture_name)	port map (Signal_list);SIGNAL LIST:-- two variants:-- variant 1: ordered list of signals as in software languages-- e.g. (In1,In2,Out1)-- variant 2: named list-- e.g. (B => In2, EQ => Out1, A => In1)Locally used nameName used incomponent declaration23A First look at VHDL:SyntaxCONFIGURATION:configuration Config_name of Entity_name is	for Architecture_name	for Instance_name: Component_name use entity	Entity_name(Architecture_name)	port map (Signal_list);	end for;	end for;end configuration Config_name;24A First look at VHDL:Example 2Declare a 3-input AND gateABCY-- 3-input AND gateentity AND3 is	port (	A,B,C: in bit;	Y: out bit);end entity AND3;architecture RTL of AND3 isbegin	Y S,Z=>U);	Gate2: component AND2 port map (X=>A,Y=>S,Z=>W);	Gate3: component AND2 port map (X=>U,Y=>B,Z=>V);	Gate4: component OR2 port map (X=>W,Y=>V,Z=>Y);end architecture Struct;A First look at VHDL:Example 3Build a 2-to-1 MUX using both a behav. as well as a structural descriptionASBYStructural descriptionASBYUVW29A First look at VHDL:Example 3Assume that we want to use the previously declared AND3, OR3 and INV for this structural description of MUXconfiguration Use3InputGates of MUX21 is	for Behav	end for;	for Struct	for Gate1:INV use entity INV(RTL)	port map (A=>X,Y=>Z);	end for;	for All:AND2 use entity AND3(RTL)	port map (A=>X,B=>Y,C=>’1’,Y=>Z);	end for;	for Gate4:OR2 use entity OR3(RTL)	port map (A=>X,B=>Y,C=>’0’,Y=>Z);	end for;	end for;end configuration Use3InputGates;EntitiesABCYAYComponentsX YZXZ30A First look at VHDL:Test benchHow can we verify the circuit that we made?We have to apply representative stimulito the circuitand check whether the outputs are correctA VHDL ‘test bench’ can be considered to be the top level of a designIt instantiates the Design Under Test (DUT)applies stimuli to itchecks whether the stimuli are correctorcaptures the outputs for visualisation in a waveform viewer31A First look at VHDL:Test benchCreate a test bench for the behavioral version of the MUXMUX21ABYSentity Testbench isend entity Testbench;Testbench isself-contained:no portsarchitecture BehavTest of Testbench is	Signal In1,In2,Select,Out : bit;begin	DUT: entity MUX21(Behav) port map (In1, In2, Select, Out);	Stimulus: process is	begin	In1 A, 1 downto 0 => C, 2 => B);Z A, 2 => B, others => C);T ‘0’); -- initialization irrespective of width of T49Signals and Data Types:Generic constantsAllows to parameterize behaviorEnables re-use of entities in slightly changing environmentsMakes VHDL much more powerful than schematic entryGeneric constants need to have a value at synthesis time!entity General_mux is	generic (width : integer);	port (	Input : in std_logic_vector (width - 1 downto 0);	Select : in integer range 0 to width - 1;	Output : out std_logic);end entity General_mux;50Generic constantsentity General_mux is	generic (width : integer);	port (	Input : in std_logic_vector (width - 1 downto 0);	Select : in integer range 0 to width - 1;	Output : out std_logic);end entity General_mux;architecture Behav of General_mux isbegin	Output Input_size)	port map (Input => A, Select => S, Output => B);...end architecture Build1;This is not valid VHDL:index is not known atdesign time! We willreplace this by validcode later!51Language based HW design:a VHDL primerIntroductionA first look at VHDLSignals and data typesVHDL operatorsConcurrent versus sequential statementsSequential construction statementsHigher performance, less portability:e.g. synthesis issues for Xilinx52Logical OperatorsList of logical operators: not, and, or, xor, nand, norPrecedence:‘not’ has highest precedenceall others have equal precedence, lower than ‘not’Logical operators are predefined for following data types: bit, bit_vector, boolean, std_logic, std_logic_vector, std_ulogic, std_ulogic_vectorA logical operator may work on an array:arrays should have same sizeelements are matched by position53Logical Operatorslibrary IEEE;use IEEE.Std_Logic_1164.All;entity Gate is	port(	A,B,C: in std_logic;	Z: out std_logic);end entity Gate;architecture Logical of Gate isbegin	Z , >, =, /=Relational operators return a booleanBoth operands need to be of the same typeA relational operator may work on an array:arrays may have different size!!They are left alligned and the number of bits equal to the smallest array are compared; the comparison is done bit by bit, from left to rightRemember: vectors of bits do not have a numerical meaning!! However, this comparison works on vectors of bits with the meaning of an unsigned integer when both vectors have equal length56Relational Operatorslibrary IEEEuse IEEE.Std_Logic_1164.All;entity Compare is	port(	A: in std_logic_vector(3 downto 0);	B: in std_logic_vector(0 to 4);	Z: out boolean);end entity Compare;architecture Relational of Compare isbegin	Z A, B => B, Z => Z);end architecture Build1;What is thevalue of Z?TRUE?FALSE?1110is compared to1011by bit positionfrom left toright;in the 2nd positionA(2) > B(1)hence (A delta cycle	convergence91ProcessProcesses and delta cycle convergence. What is the behavior of following process:Example: process (A,B,C,D) isbegin	Z 	-- sequential statements	when Value_2 =>	-- sequential statements	-- etc.end case;Example: process (A,B,C,X) isbegin	case X is	when 0 to 4 =>	Z 	Z 	Z 	Z hence a latch: when Clk is high, Q follows DSince there is no ELSE partthe previous Q value hasto be remembered for the casewhere Clk=‘0’.The synthesis tool will henceinfer a latch instead of justcombinatorial logic!!!Beware of unintended latcheswhen ELSE parts are omitted101Rising clock edgeHow do we describe a rising clock edge?Method 1: WAIT UNTILentity DFlipFlop is	port (D,Clk: in std_logic;	Q: out std_logic);end entity DFlipFlop;architecture RTL of DFlipFlop isbegin	process is	begin	wait until Clk’event and Clk=‘1’;	Q 	Output 	Output 	Output 	Output 	if (Start=‘0’) then	NextState 	NextState 	NextState 	NextState 	NextState 	NextState 	NextState 	NextState 	NextState 	NextState GSR);	if Rst = ‘1’ then	Q <= “0001”;	elseif Clk’event and Clk = ‘1’ then	Q <= Q(1 to 3) & Q(0);	endif;end architecture RTL;126Clock NetworksFoundation Express synthesizes automatically clock buffersCheck whether you do not need more clock buffers than are available in the target family127