Digital Electronics - Digital design - Dr. Pham Ngoc Nam

relativepropagation-delay: 3.2xFyVccVssxyxyx’y’x’y’Fx’VccVssxy’VccVssyxFyVccVssxyxyx’y’x’y’Fx’VccVssxy’VccVssyx=0F=1y=0x’=1VccVssxy’=1VccVssyVccVssx=0y=0x=0y=0x’=1y’=1x’=1y’=1F=1x=0F=0y=1x’=1VccVssxy’=0VccVssyVccVssx=0y=1x=0y=1x’=1y’=0x’=1y’=0F=0x=1F=0y=0x’=0VccVssxy’=1VccVssyVccVssx=1y=0x=1y=0x’=0y’=1x’=0y’=1F=0x=1F=1y=1x’=0VccVssxy’=0VccVssyVccVssx=1y=1x=1y=1x’=0y’=0x’=0y’=0F=11/88Basic logical gatesXORF=(xy), 12 TOR,relativepropagation-delay: 3.2xFyVccVssxy’xy’x’yx’yFx’VccVssxy’VccVssy1/89Contents of “Digital Design”Introduction to the courseData representationBoolean algebraLogical gatesGatesSwitching transistorBasic logical gatesGates with multiple inputs (fan-in)Multiple operators in a single gateNon-functional propertiesImplementation technologies1/90Gates with multiple inputs (fan-in)3-input NANDF=(xyz)’, 6 TOR,relativepropagation-delay: 1.8zFyVccVssxyxyFxzz1/91Contents of “Digital Design”Introduction to the courseData representationBoolean algebraLogical gatesGatesSwitching transistorBasic logical gatesGates with multiple inputs (fan-in)Multiple operators in a single gateNon-functional propertiesImplementation technologies1/92Multiple operators in a single gate2-wide 2-inputAND-OR-InvertF=(xy + zw)’, 8 TOR,relativepropagation-delay: 2.2yVccVssxyxyxwzzwzwFF1/93Multiple operators in a single gate2-wide 2-inputOR-AND-InvertF=((x+y)(z+w))’,8 TOR,relativepropagation-delay: 2.2yVccVssxyxyxwzzwzwFF1/94Contents of “Digital Design”Introduction to the courseData representationBoolean algebraLogical gatesGatesNon-functional propertiesLogical voltage levels and noise marginFan-outPower dissipationPropagation delayImplementation technologies1/95Contents of “Digital Design”Introduction to the courseData representationBoolean algebraLogical gatesGatesNon-functional propertiesLogical voltage levels and noise marginFan-outPower dissipationPropagation delayImplementation technologies1/96Logic voltage levels and noise marginFor CMOS and TTL, 0V corresponds to the logical ‘0’ and 5V to ‘1’ (ideal and in steady state)Realistically and during transition for TTL invertor:VoutVinHighLow52.40.4000.82.05LowHighVariation function of:	- temperature	- power supply voltage	- manufacturing1/97Logic voltage levels and noise marginTTL guarantees a low output level between 0V and 0.4V (=VOL) and recognizes voltages between 0V and 0.8V (=VIL) as logic ‘0’Noise up to 0.4V peak between output and next input are interpreted correctlyThe noise margin is hence VIL-VOL=0.4VTTL guarantees a high output level between 2.4V (=VOH) and 5V and recognizes voltages between 2.0V (=VIH) and 5V as logic ‘1’Noise up to 0.4V peak between output and next input are interpreted correctlyThe noise margin is hence VOH-VIH=0.4V1/98Logic voltage levels and noise marginGraphical representation of noise margin:LowLowHighHighVssVssVccVccOutputInputVOLVOHVILVIHMarginMargin1/99Contents of “Digital Design”Introduction to the courseData representationBoolean algebraLogical gatesGatesNon-functional propertiesLogical voltage levels and noise marginFan-outPower dissipationPropagation delayImplementation technologies1/100Fan-out: ‘current driven’ technologies cf. TTL, ECL, ...Fan-out: maximum number of inputs that may be connected to a single outputDepends on the current that may be delivered by the driving gate (source) (IOH) w.r.t. the current consumed by the driven gate (IIH) and on the current sinked by the driving gate (sink) (IOL) w.r.t. the current delivered by the driven gate (IIL)Fan-out = min(IOH/IIH,IOL/IIL)IOHIIHIOLIIL1/101Fan-out: ‘charge driven’ technologies cf. CMOSFan-out: maximum number of inputs that may be connected to a single outputDepends on the current that may be sourced resp. sinked by the driving gate (IOH resp. IOL) w.r.t. the capacity of the connected inputs and the connecting wire and to the switching time allowed I=dQ/dt=C.dV/dt=C.f.DV => determines maximum switching frequencye.g. based on realistic values for Xilinx Virtex:10 pF input capacity, 20 mA drive current, 0.8 pF/cm PCB connect, Vcc=3.3 VFor fan-out=3 and 10 cm PCB connect: C=3*10+0.8*10=38 pF and switching frequency = I/(C.DV)=20 mA/(38 pF * 3.3 V)=160 MHz1/102Contents of “Digital Design”Introduction to the courseData representationBoolean algebraLogical gatesGatesNon-functional propertiesLogical voltage levels and noise marginFan-outPower dissipationPropagation delayImplementation technologies1/103Power dissipationTTL dissipates continuouslyP=VCC*ICC10mW/gate1 million gates: 10 KW!!Only used when high voltages or large currents are needed (busdrivers, )CMOS dissipates only while switchingP=C.f.V2 since I=C.f.VC: proportional to chip area (trend: increase)f: trend: steep increase: 1MHz  1 GHzV: trend: steady decrease: 5  3.3  2.5  1.8  1.5  1.2  0.9Virtex example: P=38 pF*160 MHz*(3.3 V)2=66 mW per switching pin; assuming 200 pins, half of which switch concurrently, gives 6.6 W for driving the external pinsAdvanced microprocessors: 40W  Cooling!!!Is currently the limiting design factor1/104Contents of “Digital Design”Introduction to the courseData representationBoolean algebraLogical gatesGatesNon-functional propertiesLogical voltage levels and noise marginFan-outPower dissipationPropagation delayImplementation technologies1/105Propagation delay90%50%10%tPLHtPHLPropagation delay:tP=(tPLH+tPHL)/290%50%10%RisetimeFalltimeRise time > Fall time1/106Contents of “Digital Design”Introduction to the courseData representationBoolean algebraLogical gatesGatesNon-functional propertiesImplementation technologiesSSI, MSI, LSI, VLSICustom design, standard cell designGate arrayPLA, PLD, FPGA1/107Contents of “Digital Design”Introduction to the courseData representationBoolean algebraLogical gatesGatesNon-functional propertiesImplementation technologiesSSI, MSI, LSI, VLSICustom design, standard cell designGate arrayPLA, PLD, FPGA1/108SSI, MSI, LSI, VLSI (I)SSI: Small Scale Integration< 10 gates per packagegates directly connected to package pinsdesigned using transistor level designused using gate level design MSI: Medium Scale Integration10 - 100 gates per packageregisters, adders, parity generators, designed using gate level designused using RTL designLSI: Large Scale Integration100 - 10K gates per packagecontrollers, data pathsdesigned using RTL designused using behavioral level design1/109SSI, MSI, LSI, VLSI (II)VLSI: Very Large Scale Integration10K - 1M gates per packagememory, microprocessor, microcontroller, FFTdesigned using behavioral level designused using system level designULSI: Ultra Large Scale Integration???1M - ?? Gates per package2 controllers, 20 DSP processors, 16 Mbyte memory, 10 accelerators, 1 Mgate FPGA, Analog interface, RFdesigned using system level designonly one chip needed for complete application ??1/110Contents of “Digital Design”Introduction to the courseData representationBoolean algebraLogical gatesGatesNon-functional propertiesImplementation technologiesSSI, MSI, LSI, VLSICustom design, standard cell designGate arrayPLA, PLD, FPGA1/111Custom designEach transistor and each connection is designed individually as a set of rectangles.Excellent for optimal design of library elements that are re-used multiple timesCompanies design and sell such optimized libraries Has to be completely re-done each time technology changes (every 18 months!)1/112Standard cell designLibrary of standard cellseach cell is a gatestandard height, variable width, interleaved by routing channelsall inputs at the top, all outputs at the bottomFaster design of more complex building blocksSilicon foundries design and sell such optimized libraries for their processing technologyPlacement and routing1/113Standard cell designDesign FlowDesign entryPlacementRoutingSimulationTiming simulationFabrication: n masksTesting1/114Contents of “Digital Design”Introduction to the courseData representationBoolean algebraLogical gatesGatesNon-functional propertiesImplementation technologiesSSI, MSI, LSI, VLSICustom design, standard cell designGate arrayPLA, PLD, FPGA1/115Gate array designTwo-dimensional grid of identical gateseach cell is for example a 3-input NAND gatestandard height, standard width, interleaved by routing channelsall inputs at the top, all outputs at the bottomCheaper:Only the last metallisation layer is project specific1/116Gate array designDesign FlowDesign entryPlacementRoutingSimulationTiming simulationFabrication: 1 maskTestingMap all functions tothe available 3-inputNANDsTechnology mapping1/117Contents of “Digital Design”Introduction to the courseData representationBoolean algebraLogical gatesGatesNon-functional propertiesImplementation technologiesSSI, MSI, LSI, VLSICustom design, standard cell designGate arrayPLA, PLD, FPGA1/118Field-programmable designFuse programmableOne time customer programmable by selectively blowing fuses PLA: Programmable Logic ArrayPLD: Programmable Logic DeviceCPLD: Complex PLDSRAM basedFPGA: Field Programmable Gate Array (see laboratory sessions)Properties:Excellent for prototypesExcellent for medium volumes (<100K pieces/year)For SRAM based: reconfiguration (static or dynamic) possible2 Mgates @ 200 MHz (in 2000)1/119Field-programmable designPLA1/120Field-programmable designPLDDD1/121Field-programmable designCPLDAND-ORPlaneOI/OSwitch matrixI/OOAND-ORPlaneAND-ORPlaneOI/OI/OAND-ORPlaneO1/122Field-programmable designXC952166 Functional blocks (36V18 each)Flash programmable1/123Field-programmable designFPGA: XC40xxCLBCLBCLBCLBCLBCLBDirect connectionsLong linesSMSMSMSMSMSMSMSMSMSMSMSMRouting via switching matricesI/OI/OI/OI/OI/OI/OI/O1/124Field-programmable design1/125Field-programmable designFPGA: Configurable Logic Block CLB16x1LUT:Bool-functionof 4variables16x1LUT:Bool-functionof 4variablesFFGGGQFFFFFQ1/126Field-programmable design1/127Field-programmable designFPGA: Switching Matrix SMPassTOR1/128Field programmable designDesign FlowDesign entryPlacementRoutingSimulationTiming simulationDownloadingTestingTechnology mapping