Sequential circuits: With Status

ck skew problems since each flip-flop is clocked by the master clock167RegisterI3I2I1I0Q3Q2Q1Q0SymbolLoadRegistersLoadable register (without gated clock)168DQDQDQDQClkI3I2I1I0Q3Q2Q1Q0RegistersLoadable register (with gated clock) Clocks only when “CE=1” Low power dissipation: gates only switch when a newvalue is loaded Gated clocks (derived clocks) are sensitive to clockskewCE169RegistersLoadable register (with gated clock)RegisterI3I2I1I0Q3Q2Q1Q0SymbolCE170RegistersClock skew problem for gated clocks:Not all clocks of all registers change concurrentlyExpected behavior:New I3..0 appliedAt next clock edge:Clk*11, Clk*21 Q*3..0A3..0, A*3..0I3..0Real behavior:New I3..0 appliedAt next clock edge:Clk*11 A*3..0I3..0, Clk*21Q*3..0A*3..0Risk for setup violationRegister 1I3I2I1I0Register 2Q3Q2Q1Q0CEA3..0171RegistersD0Q0D1Q1IAQClkCEClkIACEGatedClkQD0Q0D1Q1IAQClkCED0Q0D1Q1IAQClkCED0Q0D1Q1IAQClkCEPossible setup or hold violation for 2nd flip-flopD0Q0D1Q1IAQClkCE172RegistersWhat causes clock skew?Gated clocksDifferent relative routing delayOn PCB and within chip: different wire lengthIn FPGA: different number of routing switchesDelay depends on many things:temperature, power supply voltage, fan-out, IC batchunder no circumstance clock skew may cause problems!!!  worst case analysis (e.g. min-delay for data path and max-delay for clock path and vice versa)173Sequential CircuitsThe flip-flop as building blockDesign of synchronous sequential circuitsDesign of asynchronous sequential circuitsBasic RTL building blocksRegistersShift registersCountersSynchronous countersAsynchronous countersRegister filesLIFO queue (push down stack)FIFO queue174Shift registersSerial-in/parallel-out shift register (SIPO)DQDQDQDQClkILQ3Q2Q1Q010SSE10S10S10SExample of utilization:	Receive register (Rx) serial port	Delay line for FIR and IIR filters175Shift registersSerial-in/parallel-out shift register (SIPO)Shift RegisterQ3Q2Q1Q0SymbolSEIL176Shift registersParallel-in/serial-out shift register (PISO)DQDQDQDQClkILQ010SSh/Ld10S10S10SExample of utilization: Transmit register (Tx) serial portI3I2I1I0CE177Shift registersParallel-in/serial-out shift register (PISO)ShiftRegisterI3I2I1I0Q0SymbolILCESh/Ld’178Sequential CircuitsThe flip-flop as building blockDesign of synchronous sequential circuitsDesign of asynchronous sequential circuitsBasic RTL building blocksRegistersShift registersCountersSynchronous countersAsynchronous countersRegister filesLIFO queue (push down stack)FIFO queue179Synchronous countersSynchronous up-counterDQDQClkQ1Q0ClearDQQ2OutputcarryHAHAHAESynchronous because all flip-flops are clocked by thesame signal180Synchronous countersClkQ1Q0Q2OutputcarryDQDQDQHAHAHAEClearClkClearEQ0Q1Q2DQDQDQHAHAHADQDQDQHAHAHADQDQDQHAHAHADQDQDQHAHAHADQDQDQHAHAHADQDQDQHAHAHADQDQDQHAHAHAGlitch!DQDQDQHAHAHADQDQDQHAHAHADQDQDQHAHAHADQDQDQHAHAHADQDQDQHAHAHADQDQDQHAHAHA181Synchronous countersSynchronous up/down-counterDQDQClkQ1Q0ClearDQQ2OutputcarryEHASHASHASDCiCoHalf adder/subtractor182Synchronous countersDesign of the Half adder/subtractorHASDciQiDicoBehavior:When ci=0 then Di=Qi (no counting)When ci=1 this section should toggleC0 has to be 1 when the next sectionhas to toggle. When should this happen?Up-count000110110001Next section togglesat 10 of this sectionDown-count001110010011Next section togglesat 01 of this section183Synchronous countersDesign of the Half adder/subtractorUp-count000110110001Next sectiontoggles at 10of this sectionDown-count001110010011Next sectiontoggles at 01of this sectionBehavior:When ci=0 then Di=Qi (no counting)When ci=1 this section should toggleC0 has to be 1 when the next sectionhas to toggle. When should this happen?Up-count000110110001Next sectiontoggles at 10of this sectionDown-count001110010011Next sectiontoggles at 01of this sectionBehavior:When ci=0 then Di=Qi (no counting)When ci=1 this section should toggleC0 has to be 1 when the next sectionhas to toggle. When should this happen?Up-count000110110001Next sectiontoggles at 10of this sectionDown-count001110010011Next sectiontoggles at 01of this sectionBehavior:When ci=0 then Di=Qi (no counting)When ci=1 this section should toggleC0 has to be 1 when the next sectionhas to toggle. When should this happen?Up-count000110110001Next sectiontoggles at 10of this sectionDown-count001110010011Next sectiontoggles at 01of this sectionBehavior:When ci=0 then Di=Qi (no counting)When ci=1 this section should toggleC0 has to be 1 when the next sectionhas to toggle. When should this happen?184Synchronous countersDesign of the Half adder/subtractor01101001ciDirQiDi00000101ciDirQici+1ciDirQiDici+1185Synchronous countersParallel loadable up/down-counterClkQ1ClearDQQ2OutputcarryEHASHASHASDCiCo01DQ01Q0DQ01I2I1I0Load186Synchronous countersBCD up-counterUp-counterI3I2I1I0Q3Q2Q1Q0ELoad0 0 0 0Compares with constant:When count equals ‘1001’ (i.e. 9), ‘0000’ is loaded at next clock edge187Synchronous countersBCD up/down-counterUp/down-counterI3I2I1I0Q3Q2Q1Q0ELoadMux0 0 0 01 0 0 110D188Sequential CircuitsThe flip-flop as building blockDesign of synchronous sequential circuitsDesign of asynchronous sequential circuitsBasic RTL building blocksRegistersShift registersCountersSynchronous countersAsynchronous countersRegister filesLIFO queue (push down stack)FIFO queue189Asynchronous countersTQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’ClkQ0Q1Q2Q3TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’TQTQTQTQClkQ3Q2Q1Q0ClearEQ’Q’Q’Q’190Sequential CircuitsThe flip-flop as building blockDesign of synchronous sequential circuitsDesign of asynchronous sequential circuitsBasic RTL building blocksRegistersShift registersCountersSynchronous countersAsynchronous countersRegister filesLIFO queue (push down stack)FIFO queue191Register filesDQWEDinClkREDoutRegister File Cell (RFC)This implementation dissipates much power due to theactive memorization of data, but does not suffer fromclock skew problems.Combining ‘WE’ with ‘Clk’ into a gated clock, we canreduce the power dissipationDQDoutWEDinClkRENote that in both cases,‘writing’ is clocked, but‘reading’ is not clocked!Needed for critical-pathcomputation...192Register filesRFCRFCRFCRFCRFCRFCRFCRFCRFCRFCRFCRFCRFCRFCRFCRFC01230123I0I1I2I3O0O1O2O32-to-4writedec2-to-4readdecWA1WA0WERA1RA0RE193Sequential CircuitsThe flip-flop as building blockDesign of synchronous sequential circuitsDesign of asynchronous sequential circuitsBasic RTL building blocksRegistersShift registersCountersSynchronous countersAsynchronous countersRegister filesLIFO queue (push down stack)FIFO queue194LIFO queue - stackTopTop-1Top-2Top-3Top-4Top-5Top-6Top-7emptyemptyemptyemptyemptyemptyemptyempty1. Reset45emptyemptyemptyemptyemptyemptyempty2. Push 451245emptyemptyemptyemptyemptyempty3. Push 124. Push 23231245emptyemptyemptyemptyempty5. Pop -> 231245emptyemptyemptyemptyemptyempty6. Push 10101245emptyemptyemptyemptyempty195LIFO queue - stackUsing left/right’ shift registerResetL/R’EnableILIRO0O7and counter for indicationempty/full196LIFO queue - stackResetL/R’EnableILIRO0O7ResetL/R’EnableILIRO0O7ResetUp/down’EnableQ3..000EnableReset’Push/pop’In0In7Out0Out7EmptyFull197LIFO queue - stackAlternative implementation: for large stacks0123Write PtrRead Ptremptyempty2345213. Push 23Does not shift!empty122345324. Push 122. Push 45emptyemptyempty4510At ‘Push’ both ptrs count up5. Pop -> 12emptyempty234521At ‘Pop’ both ptrs count down6. Push 17empty172345321. Resetemptyemptyemptyempty030=empty7. Push 5252172345030=full198LIFO queue - stackRU/D’EUp/downcounterWrite ptrSU/D’EUp/downcounterRead ptr2-to-1MUX1Kx8RAMACSR/W’D1010S8Watch timing of the enable: when RAM is not clockedbe careful not to read/write twice since the counterscount furtherReset’Push/Pop’EnableFull/emptyDatain/outNote:SET199Sequential CircuitsThe flip-flop as building blockDesign of synchronous sequential circuitsDesign of asynchronous sequential circuitsBasic RTL building blocksRegistersShift registersCountersSynchronous countersAsynchronous countersRegister filesLIFO queue (push down stack)FIFO queue200FIFO queueTopTop-1Top-2Top-3Top-4Top-5Top-6Top-7emptyemptyemptyemptyemptyemptyemptyempty1. Reset45emptyemptyemptyemptyemptyemptyempty2. Write 452345emptyemptyemptyemptyemptyempty3. Write 23122345emptyemptyemptyemptyempty4. Write 121223emptyemptyemptyemptyemptyempty5. Read -> 45571223emptyemptyemptyemptyempty6. Write 57201FIFO queueResetEnableILO0O7ResetEnableILO0O7SetUp/down’EnableQ3..0EnableReset’Read/write’In0In7Uit0Uit7EmptyFull7070S2..0S2..0Readpointer202FIFO queueAlternative implementation: for large FIFO’s0123Write PtrRead Ptremptyemptyemptyempty001. Reset2. Write 45emptyemptyempty4510Only write pointer incr. at writeemptyempty2345203. Write 23Does not shift!empty122345304. Write 12empty1223empty315. Read -> 45Only read pointer incr. at read6. Write 57571223empty01Wrap-around7. Write 165712231611Read and write pointer equal: empty or full203FIFO queuePrevious implementation indicates empty/full but does not distinguish between bothSolution:assume queue depth equals 2nread and write pointer are hence n-bit up-countersselect however an (n+1)-bit up-counter:n-LSB of read and write equal: empty/fullMSB equal: emptyMSB different: fullapply only the n-LSB as address for RAM-queueFor the stack, we also did not differentiate between empty and full; how can it be solved there? 204FIFO queueRE11-bit UpcounterWrite ptrRE11-bit UpcounterRead ptr2-to-1MUX1Kx8RAMACSR/W’D1001S8Reset’Read/Write’EnableEmptyDatain/out=?FullMSB10-LSB205