Microprocessing Systems - Chapter 2: Hardware Summary - Lê Chí Thông

t 
reading of program bytes
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• ALE (Address Latch Enable)
o Use to demultiplex the address and data bus
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• /EA (External Access) It is tied to +5V or ground.
o /EA = +5V: executes programs from internal ROM
o /EA = 0V: executes programs from external ROM
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• RST (Reset):
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• XTAL1 , XTAL2: On-chip oscillator inputs
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FIGURE 2–5 Relationship between oscillator clock cycles, states, and the machine cycle
A machine cycle is 12 oscillator periods.
Use 12 MHz crystal: a machine cycle is 1 µs
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• Vdd, Vss: Power connections
o Vdd is connected to +5V
o Vss is connected to ground (0V)
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Don’t need Bus-driver
I/O Port Structure
• Port 1, 2, and 3 have internal pull-up resistors.
• Port 0 has no internal pull-up resistors.
• Instructions that input a port bit require the ‘1’ port latch. 
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Memory Organization
• Memory
o ROM: for program (code) 
 Code memory
 External: maximum 64K
 Internal (on-chip): depend on chips
o RAM: for data 
 Data memory
 External: maximum 64K
 Internal (on-chip): depend on chips
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FIGURE 2–6 Summary of the 8031 memory spaces 
Memory Map
256-byte 64-Kbyte
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• Internal (on-chip) data memory
o Register banks (00H-1FH)
o Bit-addressable RAM (20H-2FH)
o General-purpose RAM (30H-7FH)
o Special function registers (80H-FFH)
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Bit-addressable 
RAM 
(20H-2FH)
Register banks
(00H-1FH) DPTR
Using for MUL,DIV
• Internal (on-chip) data memory:
General purpose 
RAM 
(30H-7FH)
Special function 
registers
(80H-FFH)
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• General purpose RAM
o 80 bytes from addresses 30H to 7FH
o Accessed using direct or indirect addressing modes
Ex:
Direct
MOV A, 5FH
Indirect
MOV R0, #5FH
MOV A, @R0
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• Bit-addressable RAM
o 16 bytes from (byte) addresses 20H to 2FH
o 128 bits from bit addresses 00H to 7FH
o Bit can be set, cleared, ANDed, ORed, 
Ex:
To set bit 67H
SETB 67H
or
MOV A, 2CH
ORL A, #10000000B
MOV 2CH, A
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• Register banks
o Bank 0 (default), Bank 1, Bank 2, and Bank 3
o Change register bank by selecting bits RS1 and RS0 the 
program status word
o One bank includes 8 registers: R0 through R7
Ex:
Read the contents of location 05H 
into the accumulator
MOV A, R5
or
MOV A, 05H
Write the contents of the accumulator 
into location 00H
MOV R0, A
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• Program Status Word (PSW)
• A and B registers
• Stack Pointer (SP)
• Data Pointer DPTR = DPH:DPL
• Port Registers (P0, P1, P2, P3)
• Timer Registers (TMOD, TCON, 
Timer1=TH1:TL1, Timer0 = TH0:TL0)
• Serial Port Registers (SCON, SBUF)
• Interrupt Register (IE, IP)
• Power Control Register (PCON)
Special Function Registers
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• Program Status Word (PSW)
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• A and B Register
o A (accumulator) register (Address E0H)
 The most versatile register
 Used for many operations (addition, subtraction, 
multiplication, division, Boolean bit manipulations, )
o B register (Address F0H)
 Used with the A register for multiplication and division
Ex: To multiply the 8-bit unsigned values in A and B and leaves 
the 16-bit result in A (low-byte) and B (high-byte)
MUL AB
To divide A by B and leaves the integer result in A and the 
remainder in B
DIV AB
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• Stack Pointer (SP) (Address 81H)
o Used to access the stack
o PUSH: SP increases before storing data on the stack
o POP: data is read from the stack and then SP decreases
o The reset value of SP is 07H 
 Stack is from 08H
o LIFO: Last In First Out
Ex: To set the stack beginning at 60H
MOV SP,#5FH
To store data from R1 register
into stack
PUSH 01H
To retrieve data from stack
to register R2
POP 02H
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• Stack Pointer (SP) (Address 81H)
Ex:MOV R1,#15H
MOV R3,#0FH
MOV R7,#0E9H
PUSH 01H
PUSH 03H
PUSH 07H
MOV R1,#67H
MOV R3,#0D8H
MOV R7,#63H
POP 07H
POP 03H
POP 01H
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R1 15H R3 0FH R7 E9H
0AH
09H
08H
SP=07H
0AH
09H
SP=08H 15H
07H
0AH
SP=09H 0FH
08H 15H
07H
R1 67H R3 D8H R7 63H
SP=0AH E9H
09H 0FH
08H 15H
07H
R1 15H R3 0FH R7 E9H
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• Stack Pointer (SP) (Address 81H)
Ex:MOV R1,#15H
MOV R3,#0FH
PUSH 01H
PUSH 03H
POP 01H
POP 03H
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R1 15H R3 0FH
0AH
09H
08H
SP=07H
0AH
09H
SP=08H 15H
07H
0AH
SP=09H 0FH
08H 15H
07H
R1 0FH R3 15H
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• Data Pointer (DPTR) (Addresses 82H & 83H)
o Used to access external code or data memory
o DPTR is 16-bit register, including DPH (high-byte) and DPL
(low-byte)
Ex: To write 55H into external RAM location 1000H
MOV A,#55H
MOV DPTR,#1000H
MOVX @DPTR,A
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• Port Register 
o P0, P1, P2, and P3 registers
o Used to access I/O ports
o Ports 0, 2, and 3 may not available for I/O if external memory 
is used or if some of special features are used (interrupt, )
o All ports are bit-addressable
Ex: To read data from Port 1 into A register
MOV A,P1
To write data from R7 register to Port 2
MOV P2,R7
To set bit 7 of Port 3
SETB P3.7
To clear bit 7 of Port 1
CLR P1.7 or CLR 97H
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• Timer Registers 
o 8051 contains two 16-bit timer/counters: Timer 0 & Timer 1.
o Used for timing intervals or counting events
o Timer 0 = TH0 (high-byte) & TL0 (low-byte)
o Timer 1 = TH1 (high-byte) & TL1 (low-byte)
o Timer operation is set by the Timer Mode Register (TMOD) 
and the Timer Control Register (TCON) (discussed in details 
in Chapter 4).
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• Serial Port Registers 
o 8051 contains serial port for communicating with serial 
devices such as PC (via serial port) or other ICs with serial 
interface.
o The Serial Control Register (SCON) is used to set various 
modes of operations.
o The Serial Buffer Register (SBUF) is used to transmit and 
receive data.
 Writing to SBUF loads data for transmission
 Reading SBUF accesses received data
(discussed in details in Chapter 5)
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• Interrupt Registers 
o 8051 has a 5-source, 2-priority level interrupt structure.
o The Interrupt Register (IE) is used to enable interrupts.
o The Interrupt Priority Register (IP) is used to set the priority 
level.
(discussed in details in Chapter 6)
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• Power Control Register (PCON) 
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External Memory
• When external memory is used:
o Port 0 is a multiplexed address (A0-A7) & data (D0-D7) bus.
o Port 2 is usually the high-byte of address bus (A8-A15)
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• Accessing External Code Memory
o External code memory is ROM enabled by /PSEN signal.
o Port 0 & Port 2 are unavailable as I/O ports.
o Port 0 is AD0-AD7 bus & Port 2 is A8-A15 bus.
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FIGURE 2–10 Read timing for external code memory
Timing diagram for external CODE memory access
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• Accessing External Data Memory
o External code memory is RAM enabled by /RD & /WR 
signals using MOVX instruction.
o Port 0 & Port 2 are unavailable as I/O ports.
o Port 0 is AD0-AD7 bus & Port 2 is A8-A15 bus.
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FIGURE 2–11 Timing for MOVX instruction
For external DATA memory
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• Address Decoding
o If multiple ROMs and/or RAMs are interfaced to an 8051, 
address decoding is required.
o Typically, a decoder IC such as 74HC138 is used with its 
outputs connected to the chop select (/CS) inputs on the 
memory ICs.
o Remember enable lines: /PSEN for code memory (ROM) and 
/RD & /WR for data memory (RAM)
o Accommodate up to 64KB each of ROM and RAM
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FIGURE 2–13 Address decoding
ROM RAM
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• Overlapping the External Code and Data Spaces 
o A RAM can occupy code and data memory space by using the 
following circuit.
For external CODE and DATA memory
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References
Lê Chí Thông
• I. Scott Mackenzie, The 8051 Microcontroller
• Các tài liệu trên Internet không trích dẫn hoặc không ghi tác 
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