Load and Transfer Instructions

 The Load (L) and Transfer (T) instructions enable you to

program an interchange of information between input or

output modules and memory areas, or between memory

areas.

 The CPU executes these instructions in each scan cycle as

unconditional instructions, that is, they are not affected by

the result of logic operation of a statement.

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W#16#296
+296
+0.75
or
+7.5 E-1
0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 031 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
28
= 
256 +
25
= 
32 +
23
= 
8 = 296Integer (32 Bit) =
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 1 1 1 1 0 1 0 0 0 0 0
Sign of
Real No
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 031 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
e = Exponent (8 Bit) f = Mantissa (23 Bit)
General Format of a Real Number = (Sign) • (1.f) • (2e-127)
2021222324252627 2-232-1 2-2 2-4 .....2-3
0 0 0 0
0 0 0Sign (+)
00 0 0 0 0 1 0 1 0 0 1 0 1 1 0
2 9 60
0 0 00 0 00 0 0 0 0 0
BCD
DINT
REAL
Seite 2
Date: 02.10.2014
File: PRO1_07E.7
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Examples
of Load
Load and Transfer Instructions (1)
L +5 // 16-bit constant (Integer)
L L#523123 // 32-bit constant (Double
Integer)
L B#16#EF // byte in hexadecimal form.
L 2#0010 0110 1110 0011 // 16-bit binary value
L 3.14 // 32-bit constant (Real)
MOVE
EN
IN
OUT
ENO
MB5
5
FBD
L +5
T MB5
STL
MOVE
EN
OUT
ENO
MB5
LAD
IN5
Date: 02.10.2014
File: PRO1_07E.8
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Load and Transfer Instructions (2)
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
:
:
L W#16#CAFE
L W#16#AFFE
:
:
:
X X X X X X X XC A F E
A F F E
Content of
ACCU2
Content of
ACCU1
Programm
Y Y Y Y Y Y Y YX X X X X X X X
0 0 0 0 C A F E
Date: 02.10.2014
File: PRO1_07E.9
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Load and Transfer Instructions (3)
31 23 15 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB0
31 23 15 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB1MB0
31 23 15 7 0
MB3MB2MB0 MB1
Load
L MB 0
Program
T QD 4
QD 4
QW 4
QB 4
Transfer
Contents of ACCU1
L MW 0
L MD 0
T QW 4
T QB 4
Date: 02.10.2014
File: PRO1_07E.10
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Structure of a Statement
 Statement group 1
Instruction alone
 Statement group 2
Instruction + address
Date: 02.10.2014
File: PRO1_07E.11
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Addressing
 Immediate Addressing
 Direct Addressing
 Memory Indirect Addressing
 Address Registers
 Area-Internal Register Indirect Addressing
 Area-Crossing Register Indirect Addressing
Date: 02.10.2014
File: PRO1_07E.12
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Immediate Addressing
Seite 3
Date: 02.10.2014
File: PRO1_07E.13
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Direct Addressing
Date: 02.10.2014
File: PRO1_07E.14
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Memory Indirect Addressing
Date: 02.10.2014
File: PRO1_07E.15
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Pointer Format
 Word Pointer Format
 Double Word Pointer Format
Date: 02.10.2014
File: PRO1_07E.16
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Word Pointer Format for Memory Indirect Addressing
Date: 02.10.2014
File: PRO1_07E.17
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Double Word Pointer Format for Memory Indirect Addressing
Date: 02.10.2014
File: PRO1_07E.18
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Address Registers
 Address registers 1 and 2 (AR1 and AR2) : 32-bit registers that 
accept an area-internal or area-crossing pointer for commands 
that use register-indirect addressing.
 Pointers are used in register-indirect addressing:
 Area-internal: used for area-internal access to bits, bytes, words, 
and double words in memory areas P, I, Q, M, DBX, DIX, and L
 Area-crossing: used for area-crossing access to bits, bytes, words, 
and double words in memory areas P, I, Q, M, DBX, DIX, and L
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Date: 02.10.2014
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Area-Internal Register Indirect Addressing
 two-part address
 An address identifier (ex: “LD” for “local data double word”)
 An address register and a pointer to specify byte and bit. 
The byte and bit indicate an offset, which, when added to the 
contents of the register, indicate the memory location of the 
value that the instruction is to process.
Date: 02.10.2014
File: PRO1_07E.20
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Area-Internal Register Indirect Addressing
Date: 02.10.2014
File: PRO1_07E.21
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Area-Internal Register Indirect Addressing
 Calculating the Memory Location of the Address ?
 Ex: = Q [AR1, P#1.1]
Date: 02.10.2014
File: PRO1_07E.22
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Area-Internal Register Indirect Addressing
 Area-internal register indirect addressing has only one possible 
pointer format: double word. 
Date: 02.10.2014
File: PRO1_07E.23
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Area-Internal Register Indirect Addressing
Date: 02.10.2014
File: PRO1_07E.24
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Area-Internal Register Indirect Addressing
Seite 5
Date: 02.10.2014
File: PRO1_07E.25
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Area-Crossing Register Indirect Addressing
 two-part address
 An address identifier that indicates the size of a data object 
(ex:“B” for “byte,”). The memory area is indicated in bits 24, 
25, and 26 of the address register.
 An address register and a pointer that indicate an offset 
which, when added to the contents of the address register, 
indicates the memory location of the value that is to be 
processed by the instruction. The pointer is indicated by 
P#byte.bit.
Date: 02.10.2014
File: PRO1_07E.26
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Area-Crossing Register Indirect Addressing
 Area Identification for Area-Crossing Register Indirect 
Addressing
Date: 02.10.2014
File: PRO1_07E.27
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Area-Crossing Register Indirect Addressing
 Calculating the Memory Location of the Address ?
 Ex: = [AR1, P#1.1]
Date: 02.10.2014
File: PRO1_07E.28
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Area-Crossing Register Indirect Addressing
Date: 02.10.2014
File: PRO1_07E.29
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Area-Crossing Register Indirect Addressing
 Area-crossing register indirect addressing has only one 
possible pointer format: double word.
Date: 02.10.2014
File: PRO1_07E.30
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Area-Crossing Register Indirect Addressing
Seite 6
Date: 02.10.2014
File: PRO1_07E.31
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Area-Crossing Register Indirect Addressing
Date: 02.10.2014
File: PRO1_07E.32
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Examples of how to calculate the pointer
 LAR1 P#8.2 
 A I [AR1,P#10.2] 
 Result: Input 18.4 is addressed
 L MD 0 Random pointer, e.g. P#10.5 
 LAR1 
 A I [AR1,P#10.7] 
 Result: Input 21.4 is addressed
Date: 02.10.2014
File: PRO1_07E.33
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Examples of how to calculate the pointer
Date: 02.10.2014
File: PRO1_07E.34
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Examples of how to calculate the pointer
Date: 02.10.2014
File: PRO1_07E.35
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Examples of how to calculate the pointer
Date: 02.10.2014
File: PRO1_07E.36
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Examples of how to calculate the pointer
Seite 7
Date: 02.10.2014
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Comparison of Indirect Addressing Types
Date: 02.10.2014
File: PRO1_07E.38
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Examples
 LAR2 P#20.0 ; 
 L P#24.0 ;
 LAR1;
 LAR1 MD120 ;
 LAR1 AR2;
 //Load AR2 with P#20. 0 
 //Load AR1 with 
 //Load AR1 with 
 //Load AR1 with 
Date: 02.10.2014
File: PRO1_07E.39
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Examples
 TAR2 MD140 ;
 TAR1;
 TAR1 AR2;
 //Transfer to MD140
 //Transfer to Accum1
 //Transfer to AR2 

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