Digital Electronics - Chapter 5: Analysis Combinational Circuit - Dr Le Dung

8/10/2015
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Chapter 5
Analysis Combinational Circuit
Dr. Le Dung
Hanoi University of Science and Technology
Dr. Le Dung Hanoi University of Science and Technology
From a given combinational circuit
to analysis     
• Its function 
(Truth table, Expression forms)
• Timing diagram
(Test vectors, Delay, Hazard/Glitch)  
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Dr. Le Dung Hanoi University of Science and Technology
An example (1)
2 to 4 Decoder
A0
A1
m0
m1
m2
m3
4 to 1 MUX
S1     S0
D0
D1
D2
D3
Y
a
b
c     d
f(a,b,c,d) ?
Analysis this combinational circuit
Dr. Le Dung Hanoi University of Science and Technology
An example (2)
4 to 1 MUX
S1     S0
D0
D1
D2
D3
Y
Modular understanding
2 to 4 Decoder
A0
A1
m0
m1
m2
m3
A1 A0 m0 m1 m2 m3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
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Dr. Le Dung Hanoi University of Science and Technology
An example (3)
Æ Truth table Æ Expression forms
c d a b f
0 0 0 0 1
f=Y=D0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
f=Y=D1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
f=Y=D2
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
f=Y=D3
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Æ f  =  Σ (0, 5, 10, 15)  =   Σ (0, 5, 10, 15)
cdab abcd
f = abcd + abcd + abcd + abcd
Dr. Le Dung Hanoi University of Science and Technology
An example (4)
Æ Expression forms
= abcd + abcd + abcd + abcd
c d F = Y =
0 0 D0 = m0 = a’b’ 
0 1 D1= m1 = a’b 
1 0 D2= m2 = ab’ 
1 1 D3= m3 = ab 
Æ f =  m0.cd  + m1.cd + m2.cd + m3.cd
= (a ~ c)(b~ d) = (a + c) + (b + d)Ç
√
Ç
√
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Dr. Le Dung Hanoi University of Science and Technology
An example (5)
Timing diagram with no delay
a
b
d
c
ff = (a ~ c)(b~ d)
Test vectors : abcd = 0000Æ1000Æ1010Æ1110Æ1111Æ0111Æ0101Æ0100Æ0000
Dr. Le Dung Hanoi University of Science and Technology
An example (6)
Timing diagram with delay
a
b
d
c
f
m1 = D1
m0 = D0
Test vectors : abcd = 0000 Æ 0100Æ0110Æ0100Æ0101
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Dr. Le Dung Hanoi University of Science and Technology
Static Hazard /Glitch
• Hazard condition: A single variable change causes a
momentary output change when no output change
should occur.
• Glitch: The momentary output change
= unwanted transient pulse
+ Static 1‐hazard = glitch 1Æ0Æ1 (in SOP )
+ Static 0‐hazard = glitch 0Æ1Æ0 (on POS)
• Cause: different delay in two paths (see Example)
• Solution: Adding redundant terms (product terms or sum terms)
Dr. Le Dung Hanoi University of Science and Technology
An example of static 1‐hazard
a
c
b
A
B
A
B
Y X1
Y X2
A
B
Y = f
c’
AND 2
OR 2
AND 2
INV
a = b = 1
c
X2
X1
f
Static 1‐hazard = glitch
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Dr. Le Dung Hanoi University of Science and Technology
Removing static 1‐hazard
A
B
A
B
A
B
A
B
C
Y X1
Y X2
Y X3
a
c
b
Y f
A
AND 2
AND 2 A
OR 3
AND 2
Redundant term
= consensus term 
Static 
hazard
free 
Dr. Le Dung Hanoi University of Science and Technology
Dynamic hazard
Dynamic Hazard on 0 Æ 1 Dynamic Hazard on 1 Æ 0
• A dynamic hazard is the possibility of an output changing
more than once as a result of a single input change
• Cause: different delay in multiple paths
• Any circuit that is static hazard free is also dynamic 
hazard free
• Any circuit dynamic hazard free
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Dr. Le Dung Hanoi University of Science and Technology
An example of dynamic hazard (1)
Dr. Le Dung Hanoi University of Science and Technology
An example of dynamic hazard (2)
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Dr. Le Dung Hanoi University of Science and Technology
An example of dynamic hazard (3)
Dr. Le Dung Hanoi University of Science and Technology
Function hazard
• Function hazards are non‐solvable hazards which occurs
when more than one input variable changes at the same time.
• Function hazards can not be logically eliminated with actual 
specification of the circuit. The only real way to avoid such 
problems is to restrict the changing of input variables so that 
only one input should change at any given time.
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Dr. Le Dung Hanoi University of Science and Technology
Hazard‐free design
• Hazards are hard to detect by hand: importance of 
simulation
• The danger for hazards increases when rise times and fall 
times are not equal 
• Are hazards a problem?
‰ For synchronous circuits, they are not
‰ Unless they control the clock of a memory element
‰ For asynchronous circuits, they always are a problem