Bài giảng Các hệ thống tin học công nghiệp - Chương 4: Programmable Controllers

tatus word:
• JBI Jump if BR = 1
• JNBI Jump if BR = 0
• JO Jump if OV = 1
• JOS Jump if OS = 1
¾ The following jump instructions interrupt the flow of logic in your 
program based on the result of a calculation:
• JZ Jump if Zero
• JN Jump if Not Zero
• JP Jump if Plus
• JM Jump if Minus
• JPZ Jump if Plus or Zero
• JMZ Jump if Minus or Zero
• JUO Jump if Unordered
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‰ Integer Math Instructions (7th)
¾ Description: The math operations combine the contents of 
accumulators 1 and 2. The result is stored in accumulator 1. The
old contents of accumulator 1 is shifted to accumulator 2. The 
contents of accumulator 2 remains unchanged.
¾ In the case of CPUs with four accumulators, the contents of 
accumulator 3 is hen copied into accumulator 2 and the contents 
of accumulator 4 into accumulator 3.
¾ The old contents of accumulator 4 remains unchanged.
¾ Using integer math, you can carry out the following operations 
with two integer numbers (16 and 32 bits):
• +I Add ACCU 1 and ACCU 2 as Integer (16-bit)
• -I Subtract ACCU 1 from ACCU 2 as Integer 
(16-bit)
• *I Multiply ACCU 1 and ACCU 2 as Integer (16-
bit)
• /I Divide ACCU 2 by ACCU 1 as Integer (16-bit)
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• + Add Integer Constant (16, 32 Bit)
• +D Add ACCU 1 and ACCU 2 as Double Integer (32-bit)
• -D Subtract ACCU 1 from ACCU 2 as Double Integer (32-bit)
• *D Multiply ACCU 1 and ACCU 2 as Double Integer (32-bit)
• /D Divide ACCU 2 by ACCU 1 as Double Integer (32-bit)
• MOD Division Remainder Double Integer (32-bit)
¾See also Evaluating the Bits of the Status Word 
with Integer Math Instructions.
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‰ Floating-point Math Instructions (8th)
¾ Description: The math instructions combine the contents of 
accumulators 1 and 2. The result is stored in accumulator 1. The
old contents of accumulator 1 is shifted to accumulator 2. The 
contents of accumulator 2 remains unchanged.
¾ In the case of CPUs with four accumulators, the contents of 
accumulator 3 is copied into accumulator 2 and the contents of 
accumulator 4 into accumulator 3.
¾ The old contents of accumulator 4 remains unchanged.
¾ The IEEE 32-bit floating-point numbers belong to the data type 
called REAL.
¾ You can use the floating-point math instructions to perform the 
following math
¾ instructions using two 32-bit IEEE floating-point numbers:
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• +R Add ACCU 1 and ACCU
• -R Subtract ACCU 1 from ACCU 2
• *R Multiply ACCU 1 and ACCU 2
• /R Divide ACCU 2 by ACCU 1
¾Using floating-point math, you can carry out the 
following operations with one 32-bit IEEE floating-
point number:
• ABS Absolute Value
• SQR Generate the Square
• SQRT Generate the Square Root
• EXP Generate the Exponential Value
• LN Generate the Natural Logarithm
• SIN Generate the Sine of Angles
• COS Generate the Cosine of Angles
• TAN Generate the Tangent of Angles
• ASIN Generate the Arc Sine
• ACOS Generate the Arc Cosine
• ATAN Generate the Arc Tangent
¾See also Evaluating the Bits of the Status Word.
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‰ Load and Transfer Instructions (9th)
¾ Description: The Load (L) and Transfer (T) instructions enable 
you to program an interchange of information between input or 
output modules and memory areas, or between memory areas. 
The CPU executes these instructions in each scan cycle as 
unconditional instructions, that is, they are not affected by the 
result of logic operation of a statement. The following Load and
Transfer instructions are available:
• L Load
• L STW Load Status Word into ACCU 1
• LAR1 AR2 Load Address Register 1 from Address 
Register 2
• LAR1 Load Address Register 1 with Double 
Integer (32-bit Pointer)
`
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• LAR1 Load Address Register 1 from ACCU 1
• LAR2 Load Address Register 2 with Double 
Integer (32-bit Pointer)
• LAR2 Load Address Register 2 from ACCU 1
• T Transfer
• T STW Transfer ACCU 1 into Status Word
• TAR1 AR2 Transfer Address Register 1 to Address 
Register 2
• TAR1 Transfer Address Register 1 to Destination 
(32-bit Pointer)
• TAR2 Transfer Address Register 2 to Destination 
(32-bit Pointer)
• TAR1 Transfer Address Register 1 to ACCU 1
• TAR2 Transfer Address Register 2 to ACCU 1
• CAR Exchange Address Register 1 with Address 
Register 2
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‰Program Control Instructions (10th)
¾Description: The following instructions are available 
for performing program control instructions:
• BE Block End
• BEC Block End Conditional
• BEU Block End Unconditional
• CALL Block Call
• CC Conditional Call
• UC Unconditional Call
• Call FB
• Call FC
• Call SFB
• Call SFC
• Call Multiple Instance
• Call Block from a Library
• MCR (Master Control Relay). Important Notes on Using MCR 
Functions
• MCR( Save RLO in MCR Stack, Begin MCR
• )MCR End MCR
• MCRA Activate MCR Area
• MCRD Deactivate MCR Area
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‰Shift and Rotate Instructions (11th)
¾11.1 Shift Instructions
ƒ Description: You can use the Shift instructions to move the 
contents of the low word of accumulator 1 or the contents of 
the whole accumulator bit by bit to the left or the right (see 
also CPU Registers). Shifting by n bits to the left multiplies 
the contents of the accumulator by “2 n ”; shifting by n bits to 
the right divides the contents of the accumulator by “2 n ”. 
For example, if you shift the binary equivalent of the decimal 
value 3 to the left by 3 bits, you end up with the binary 
equivalent of the decimal value 24 in the accumulator. If you 
shift the binary equivalent of the decimal value 16 to the right
by 2 bits, you end up with the binary equivalent of the 
decimal value 4 in the accumulator.
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The number that follows the shift instruction or a value in the low 
byte of the low word of accumulator 2 indicates the number of bits 
by which to shift. The bit places that are vacated by the shift 
instruction are either filled with zeros or with the signal state of the 
sign bit (a 0 stands for positive and a 1 stands for negative). The bit 
that is shifted last is loaded into the CC 1 bit of the status word. The 
CC 0 and OV bits of the status word are reset to 0. You can use 
jump instructions to evaluate the CC 1 bit. The shift operations are 
unconditional, that is, their execution does not depend on any 
special conditions. They do not affect the result of logic operation.
¾The following Shift instructions are available:
• SSI Shift Sign Integer (16-bit)
• SSD Shift Sign Double Integer (32-bit)
• SLW Shift Left Word (16-bit)
• SRW Shift Right Word (16-bit)
• SLD Shift Left Double Word (32-bit)
• SRD Shift Right Double Word (32-bit)
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‰ 11.2 Rotate Instructions
¾ Description: You can use the Rotate instructions to rotate the 
entire contents of accumulator 1 bit by bit to the left or to the right 
(see also CPU Registers). The Rotate instructions trigger 
functions that are similar to the shift functions described in 
Section 14.1. However, the vacated bit places are filled with the 
signal states of the bits that are shifted out of the accumulator. 
The number that follows the rotate instruction or a value in the
low byte of the low word of accumulator 2 indicates the number 
of bits by which to rotate. Depending on the instruction, rotation 
takes place via the CC 1 bit of the status word. The CC 0 bit of
the status word is reset to 0. 
¾ The following Rotate instructions are available:
• RLD Rotate Left Double Word (32-bit)
• RRD Rotate Right Double Word (32-bit)
• RLDA Rotate ACCU 1 Left via CC 1 (32-bit)
• RRDA Rotate ACCU 1 Right via CC 1 (32-bit)
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‰Timer Instructions (12th)
¾Description: You can find information for setting and 
selecting the correct time under Location of a Timer in 
Memory and components of a Timer. The following 
timer instructions are available:
ƒ FR Enable Timer (Free)
ƒ L Load Current Timer Value into ACCU 1 as Integer
ƒ LC Load Current Timer Value into ACCU 1 as BCD
ƒ R Reset Timer
ƒ SD On-Delay Timer
ƒ SE Extended Pulse Timer
ƒ SF Off-Delay Timer
ƒ SP Pulse Timer
ƒ SS Retentive On-Delay Timer
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‰Word Logic Instructions (13th) 
¾ Description: Word logic instructions compare pairs of words (16 
bits) and double words (32 bits) bit by bit, according to Boolean 
logic. Each word or double word must be in one of the two 
accumulators. For words, the contents of the low word of 
accumulator 2 is combined with the contents of the low word of 
accumulator 1. The result of the combination is stored in the low 
word of accumulator 1, overwriting the old contents. For double 
words, the contents of accumulator 2 is combined with the contents 
of accumulator 1. The result of the combination is stored in 
accumulator 1, overwriting the old contents.
¾ If the result does not equal 0, bit CC 1 of the status word is set to 
"1". If the result does equal 0, bit CC 1 of the status word is set to 
"0".
¾ The following instructions are available for performing Word Logic 
operations:
ƒ AW AND Word (16-bit)
ƒ OW OR Word (16-bit)
ƒ XOW Exclusive OR Word (16-bit)
ƒ AD AND Double Word (32-bit)
ƒ OD OR Double Word (32-bit)
ƒ XOD Exclusive OR Double Word (32-bit)
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‰ Accumulator and Address Register Instructions 
(14th)
¾ Description: The following instructions are available to you for 
handling the contents of one or both accumulators:
ƒ TAK Toggle ACCU 1 with ACCU 2
ƒ PUSH CPU with Two ACCUs
ƒ PUSH CPU with Four ACCUs
ƒ POP CPU with Two ACCUs
ƒ POP CPU with Four ACCUs
ƒ ENT Enter ACCU Stack
ƒ LEAVE Leave ACCU Stack
ƒ INC Increment ACCU 1-L-L
ƒ DEC Decrement ACCU 1-L-L
ƒ +AR1 Add ACCU 1 to Address Register 1
ƒ +AR2 Add ACCU 1 to Address Register 2
ƒ BLD Program Display Instruction (Null)
ƒ NOP 0 Null Instruction
ƒ NOP 1 Null Instruction